[A83] Re: LD A,R ; LD R,A

To: assembly-83@lists.ticalc.org
Subject: [A83] Re: LD A,R ; LD R,A
From: Martin Virt <martin.virt@gmx.at>
Date: Sun, 15 Jul 2001 02:49:37 +0200
In-Reply-To: <3.0.5.32.20010714165851.00824930@pop.snet.net>
References: <5.0.2.1.0.20010714231618.00a05140@pop.gmx.de> <0d11f4140180e71NET013S@hetnet.nl>
Reply-To: assembly-83@lists.ticalc.org




>Wouldn't this be why when you yank all the battereis your memory dies?  THe
>power might be less, as you can keep it alive through the link port, but
>the only ything that requires zero power in the ROm chip, which we know has
>the downside of 1M erase cycles.

Perhaps I'm misinterpreting your question ...
Both SRAM and DRAM are volatile. The difference between those is that in 
SRAM the bits need to be set just once and the state won't change until you 
change it or you switch off the computer, whereas DRAM has to be 
continually "reminded" that the bits are in their respective states. You 
still have to supply *both* types of RAM with power. And both of them will 
lose the information when you cut the power supply. Flash-ROM is a 
different thing altogether.
Think of the bits in DRAM as a bunch of guys you continually have to wake 
up and remind that they've got to do their job.

MaV

References:

[A83] Re: LD A,R ; LD R,A

From: Martin Virt <martin.virt@gmx.at>

[A83] Re: LD A,R ; LD R,A

From: "Henk Poley" <HPoley@DDS.nl>

[A83] Re: LD A,R ; LD R,A

From: Gavin Olson <gtolson@snet.net>