[A83] Re: LD A,R ; LD R,A

To: <assembly-83@lists.ticalc.org>
Subject: [A83] Re: LD A,R ; LD R,A
From: "Henk Poley" <HPoley@DDS.nl>
Date: Sat, 14 Jul 2001 19:53:06 +0200
Reply-To: assembly-83@lists.ticalc.org


> Van: Peter-Martijn Kuipers <hyper@hysoft-automation.com>
> 
> Does this mean that the R register can be freely used, or are there 
> other less obvious uses for?

>From AsmGuru (found the same info also on other places):

<<Q-1: I AND R REGISTERS.  What they do.

I is the Interrupt page address register [..]

R is the memory Refresh register.  The Z-80 CPU contains a memory refresh
counter to enable dynamic memories to be used with the same ease as static
memories. Seven bits of this 8 bit register are automatically incremented
after each instruction fetch. The eight bits will remain as programmed with
the LD R,A instruction.>>

So you can use the R register to 'store' something, but only if that's one
bit...

<<The data in the refresh counter is sent out on the lower portion of the
address bus along with a refresh control signal while the CPU is decoding
and executing the instruction. The programmer can load the R register for
testing purposes, but this register is normally NOT used by the programmer.
During refresh, the contents of the I register are placed on the upper 8
bits of the address bus.>>

The last thing told here doesn't apply to the Ti's, they only have stactic
RAM.

I don't really understand in what way the R register is usefull for dynamic
memories (nor what dynamic memories exactly are).

	Henk Poley

Follow-Ups:

[A83] Re: LD A,R ; LD R,A

From: "Michael Vincent" <hookman@worldnet.att.net>

[A83] Re: LD A,R ; LD R,A

From: Martin Virt <martin.virt@gmx.at>