[A83] Re: LD A,R ; LD R,A

To: assembly-83@lists.ticalc.org
Subject: [A83] Re: LD A,R ; LD R,A
From: Gavin Olson <gtolson@snet.net>
Date: Sat, 14 Jul 2001 16:58:51 -0400
In-Reply-To: <5.0.2.1.0.20010714231618.00a05140@pop.gmx.de>
References: <0d11f4140180e71NET013S@hetnet.nl>
Reply-To: assembly-83@lists.ticalc.org


>I'm not sure about the following, but this might have been the main reason 
>for SRAM on TI's calcs: DRAMs need a steady supply of electrical charges to 
>keep information and that drains the batteries.


Wouldn't this be why when you yank all the battereis your memory dies?  THe
power might be less, as you can keep it alive through the link port, but
the only ything that requires zero power in the ROm chip, which we know has
the downside of 1M erase cycles.

Follow-Ups:

[A83] Re: LD A,R ; LD R,A

From: Martin Virt <martin.virt@gmx.at>

References:

[A83] Re: LD A,R ; LD R,A

From: "Henk Poley" <HPoley@DDS.nl>

[A83] Re: LD A,R ; LD R,A

From: Martin Virt <martin.virt@gmx.at>