[TI-H] Re: TI-89 HW2 overclocking

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[TI-H] Re: TI-89 HW2 overclocking

NO fuss, that's what this less trafficed list is all about.  Now where 
the heck are we?

B.A. Baracus wrote:

> Sorry, I seem to have generated some confusion by talking about both HW1
> and HW2 hardware.
>
> On Mon, 24 Feb 2003 14:09:52 +0100, Olle Hedman <alh@home.se> wrote:
>
>> Yes, you can see it as that. The minimum number of cycles per 
>> instruction is 4, so only each 4th cycle could generate bus activity.
>
>
> Is this true of both HW1&2?
>
>> According to Johan Borg 
>> (http://d188.ryd.student.liu.se/ftp/calculator/ti89/tech/overclocking.txt) 
>>
>>
>>
>> it is because of some design of the curcuitry that keeps CS (Chip 
>> Select) active for too short time when doing byte accesses.I don't 
>> see why there would be any reason for it do be shorter then word 
>> accesses, since they still are the same speed.
>> But thats the way it is. So byte accesses fail over ~20MHz on HW1.
>
>                                                      ^^^^^^
>
>>
>> I quote some:
>> -----
>>
>> why only ~15MHz?
>
>           ^^^^^^
>
>>
>> the uP-chip can run at up to ~30MHz or so, but the RAM cant.
>>
>> the time byte-CS is active when a byte is written is much shorter
>> than the time for read or word-write, and when the frequency is 
>> incresed, that time soon becomes too short.
>> the OS actually boots with quite high frequencys, because most writes 
>> are word-writes, however doing anything will fail, and any text 
>> printed will be more or less wrong.
>
>
> This part seems to be a bit muddled to me (perhaps because I don't have
> much experience with SRAMs/microprocessors). I gather that, for some 
> reason,
> the CPU tries to write _bytes_ too quickly at more than 15MHz (or 
> 20MHz?).
>
> Now, I'm looking at the datasheet for the Toshiba 55V1001A SRAM chip for
> the HW2 (http://www.toshiba.com/taec/components/Datasheet/V1001a.pdf).
>
> I don't see anything called Chip Select, however, under Write Cycle, I 
> see
> the following:
>
> Write Cycle Time            min 85ns
> Write Pulse Width            min 60ns
> Chip Enable to End of Write    min 75ns
>
> Is one of these the relevant value that is being exceeded by the 
> calculator
> that is preventing overclocking beyond 15~20MHz?
>
>
>> in order to make the CPU run at >20MHz R12 must be redused too
>
>
> (btw, anyone know what the equivalent HW2 resistor for HW1's R12 is? and
> approximately what it would be reduced to to go >20MHz in combination 
> with
> an x pF capacitor?)
>
>
References: