[TI-H] Re: TI-89 HW2 overclocking
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[TI-H] Re: TI-89 HW2 overclocking
B.A. Baracus wrote:
> On Mon, 24 Feb 2003 12:56:46 +0100, Olle Hedman <alh@home.se> wrote:
>
>> The SRAM access speed doesn't do anything to the speed of the calc.
>> Only for how high you can overclock it.
>> 85 ns gives a max bus frequency of 11.7 MHz, and as far as I
>> remember, a 12 MHz 68000 would have a bus frequecy of about 3MHz
>> maybe I calculated a bit wrong, but the access speed of ram doesn't
>> matter for system speed unless its slower then the processor.
>
>
> Hmm, how did you calculate the bus speed? Is the m68k running at a 4X
> bus multiplier? And if this is the case, why does the top overclocking
> speed appear to be 20MHz? (perhaps some other component than the RAM is
> the limiting factor?)
>
Yes, you can see it as that. The minimum number of cycles per
instruction is 4, so only each 4th cycle could generate bus activity.
According to Johan Borg
(http://d188.ryd.student.liu.se/ftp/calculator/ti89/tech/overclocking.txt)
it is because of some design of the curcuitry that keeps CS (Chip
Select) active for too short time when doing byte accesses.I don't see
why there would be any reason for it do be shorter then word accesses,
since they still are the same speed.
But thats the way it is. So byte accesses fail over ~20MHz on HW1.
I quote some:
-----
why only ~15MHz?
the uP-chip can run at up to ~30MHz or so, but the RAM cant.
the time byte-CS is active when a byte is written is much shorter
than the time for read or word-write, and when the frequency
is incresed, that time soon becomes too short.
the OS actually boots with quite high frequencys, because most writes
are word-writes, however doing anything will fail, and any text
printed will be more or less wrong.
in order to make the CPU run at >20MHz R12 must be redused too
one way to fix this could be by adding some logic (like 2 D-latches and
some gates or something should to it) to extend the time byte-CS is active,
or making the main oscillator stop for some short time when a bytewrite is
detected (pin18 xor pin19 =1 on the CPU-chip)
another would be to use a waitstate for the RAM,
this does ofcourse makes the speedup much less when executing
from RAM also, and the waitstates for the RAM is reseted by the OS from
time to time, but the later can ofcourse be eliminated, this is probbably
the best method, as it is quite simple, and all execution in the flashrom
can be speeded up significantly.
the third metod could be to rearange the ram into byte-wide,
ti92's have only one bank of ram installed can be clocked to ~30M,
a problem however is that the OS (probably) set the bit that controlls
wether the connected ram is byte or word wide, and does so in the boot-loader
(the first 64k, which can only be written if the writeprotection in the
ROM-chip is disabled, by reconnecting a pin.
this method would also reduse the speed when reading/executing from RAM,
and is probbably more work than the previous one.
in case you havnt seen it, a pinout for the CPU with most pins identified,
and a description of the control-registers in the CPU (like the one you
set the number of wait-states in) can be found at http://alh.dhs.org/ti89/
----
That Url is wrong though. My site now is at http://www.ti89hardware.tk/ until I find myself some decent domain. (or comes around to installing IPv6)
--Olle
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