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TI-86 RAM Layout


        TI-86 RAM LAYOUT
        ----------------



                 MEMORY RAM MAP
                 --------------


  0000h       -------------------------
  (ASIC)     |                         |
             |   ROM PAGE 0            |
             |                         |
  4000h      |-------------------------|
             |                         |
             |   SWAPPED ROM PAGE(1-F) |
             |                         |
  8000h      |------------------------ |
             |                         |
             |   SWAPPED RAM PAGE (1-7)|
             |                         |
  C000h      |-------------------------|
             |                         |
             |   STATIC RAM PAGE (0)   |
             |                         |
              -------------------------

                RAM PAGE 0 (16k)    - not paged
 0C000h  -------------------------
 (ABS)  |                         |
        |  system memory          |
        |                         |
        |-------------------------|
        | INTER BANK RAM CACHE    |
        |-------------------------|
        |  RESEVERED RAM FOR      |
        |  ASSEMBLY LANGUAGE      |
        |  PROGRAMMING ~ 8k       |
        |-------------------------|
        |       ^                 |
        |       :                 |
        |  hardware stack         |               RAM PAGES 2 - 7 (96K)
 0FC00h |-------------------------|    14000  -------------------------
        |  display ram            |    (ABS) |   USER MEMORY           |
 0FFFFh  -------------------------           |        |                |
                                             |        v                |
              RAM PAGE 1 (16K)               |.........................|
10000    -------------------------  FPBASE   |   TEMP MEMORY           |
(ABS)   |  floating point stack   |          |        |                |
        |       :                 |          |        v                |
        |       v                 |          |.........................| ---
        | . . . . . . . . . . . . | *FPS     |         ^               | 1  |
        |                         |          |         |               | 6  |
        | FREE EXEC RAM           |          |   TEMPS SYM TABLE       | K  |
        | . . . . . . . . . . . . | *OPS     |.........................|    |
        |       ^                 |          |         ^               | M  |
        |       :                 |          |         |               | A  |
        |  operator stack         |          |   USER SYM TABLE        | X  |
13FFF    -------------------------  OPBASE    ------------------------- ----
(ABS)



        - The TI-86 uses a paged RAM design inorder to allow the
          system to use more than 32k of RAM.

        - 16k of RAM at C000h - FFFFh is static RAM that is always
          directly addressable.

        - The 16k address space at 8000h - BFFFh is used for swapping
          in 1 of 7 other 16k RAM pages.

        - For ease of coding the RAM swapping was made transparent by
          overlaying an 'absolute address' space over the RAM pages.

        - Below is a chart showing how the absolute address is decoded
          into a RAM PAGE and an offset.



             ABS = ABSOLUTE ADDRESS

         ABS             RAM PAGE    ASIC ADDR
         ----            --------    ---------
         0C000-0FFFF        0        C000-FFFF  - always available

         10000-13FFF        1        8000-BFFF  - these are all paged
         14000-17FFF        2        8000-BFFF
         18000-1BFFF        3        8000-BFFF
         1C000-1FFFF        4        8000-BFFF
         20000-23FFF        5        8000-BFFF
         24000-27FFF        6        8000-BFFF
         28000-2BFFF        7        8000-BFFF


        - Some results from implementing a paged RAM system :

                - all memory accesses and moves involving paged RAM
                  cannot be done directly, system routines are required
                  to handle these operations.

                - loss of efficiency.

                - a 3 byte address must be used instead of 2 byte.

TI-86 Assembly Programming

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