92 929292 929292 92 92 929292 92 92 92 92 92 92 92 92 9292 92 92 92 929292 92 92 92 92 92 92 92 92 92929292 929292 92929292 92 929292 Introduction : -------------- This library is intended to allow control of the I²C bus in single master mode via the TI92 serial link port. The I²C bus is a 2-wire serial bus protocol invented by Philips to easily interconnect Integrated Circuits (I²C stands for Inter Integrated Circuits) in applications where bitrate doesn't need to be high (like in human/machine interfaces, low multiplexing rate LCDs, etc). Why the choice of the I²C bus ? : First, I needed to choose a bus which could easily be interfaced with only the two wires plus ground available at the TI's link port and in serial mode. I know only four one or two wire busses, and I chose the I²C bus for the following reasons : - The basic 'open drain' configuration is the same for I²C bus and TI's link port; - The I²C protocol has been used in many application and is considered as a serial bus standard (most TV sets use this protocol for communication between IR receiver, tuner, etc); - The low number of wires (only two for the protocol itself) and the integration of ICs which do not need supplementary 'glue logic' reduces significantly the costs and allows high flexibility. - The components themselves are easily available everywhere. They are quite expensive, but do not need any interfacing logic, so the total cost is lower. - The bus is plug and play ! :) Basics of the i2c protocol : The clock signal is all the time controlled by the master. Send procedure : - Master initiates the protocol -> all connected ICs listen - Master sends adress of the slave -> adressed IC acknowledges, all other IC's stay idle until the bus is released - Master sends an arbitrary number of bytes -> slave acknowledges each byte, if not transfert should be stopped - Master terminates the protocol Get procedure : - Master initiates the protocol -> all connected ICs listen - Master sends adress of the slave +1 -> adressed IC acknowledges, all other IC's stay idle until the bus is released - Slave sends an arbitrary number of bytes -> Master acknowledges each byte - Slave sends one (last) byte -> Master does not acknowledge -> Slave must stop communication - Master terminates the protocol To make the difference between send and get order, the adresses of the ICs are all even : adress as is is used for transfert from master to slave, and adress+1 is used for transfert from slave to master. Library features : ------------------ The library allows all the basic operations on the bus : Start and Stop condition, Adressing of hardware and bidirectionnal data transfert. However, it only allows the bus to work in single master mode, the TI92 beeing the master. (for details on functions, see 'i2clib.h') The library is provided with two function 'i2csend' and 'i2cget' to allow the use of the bus in TI-BASIC too. Syntax for these functions : i2csend(l) where l is the list of bytes to be sent through the bus. Returns true if the operation suceeded, and false if not. i2cget({ad,nb}) Returns a list containing nb bytes get from the IC at the adress ad (don't forget to add 1 to base adress). If the transfert failed, the list returned is empty. The future : ------------ - A better i2cget function ? Implement the arbitration procedure and multi-master capability History : --------- 05/05/1999 : v0.1 : First release, works quite well 02/08/1999 : v0.1.1 : Start function doesn't deactivate interrupts anymore Me : ---- You can join me by e-mail at this adress : bubuw@multimania.com I'd be pleased to receive any suggestion, ideas to improve this program or for another program. For more TI92 related content, program updates, source code, and other programming / electronics / music stuff, check my site at: http://www.multimania.com/bubuw Credits : --------- This program was written using Fargo program editor, a very nice and useful tool by Benoit SCHERRER - p.c.scherrer@wanadoo.fr