Re: TI-H: General questions with a possibly big im
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Re: TI-H: General questions with a possibly big im
>I see. TheNMOS/CMOS thing had to deal with something is saw in the
>Zilog Z80 databooks. The CMos versions can be single stepped with the
>clock. taht woudlbe a big help with somehhardware investigations.
That's because the CMOS version is statically designed... NMOS depends
on dynamic delays and therefore cannot run until you reach a minimum
clock speed. NMOS also uses about 1000x more power, too :).
>anyway...
>about the port space: it doesnt matter how much TI built the port space
>because the Z80 (if it is indeed the Z80 design, as you said it may not
>be:( )
Well it's definitely not the original Z80 stuck inside a new chip with
stuff around it, that's for sure.
>immediatley puts the IO address used in the OUt otr IN
>instruction directly on the lower half of thedirectly on teh address bus
>aout of the processor. this could be checked along witht he IORQ line,
>which goes low ehn the IN or OUT instruction sare being processed, and
>the n the device could do its stuff. it puts the IO address on the
>lower 8 bits of the address lines, so that is why there is the max 256.
>But, without the IORq lin, my methos is finished:(((((((((
Heh yeah they likely don't bring the IORQ line out, and even if they
did, it would be impossible to test without an expensive logic
analyzer as well as an expensive QFP logic probe which can't be bought
at rat shack :).
Here's one of the methods I figured out to give a CPU-speed I/O port:
Replace the SRAM chip with an array of chips that redirects only
certain addresses to the port. This is pretty difficult to do with
some standard 74HC parts, but it would be relatively easy with a $10
CPLD or FPGA (programmable "gate arrays") from Xilinx/altera/lattice,
etc. This extra PCB you replace the SRAM with would then consist of
two chips: the FPGA and a new battery backed SRAM chip that is larger
than the original 32k, or even multiple SRAM chips. The largest
single SRAM chips are 512k so this could be your target. You would
have to be careful about power requirements though, because you may
start sucking 50 to 60 milliamps which the TI-85 wouldn't like. But
if you're smart about the design you can keep the power consumption
down to the point where battery life is unchanged.
This replacement module works on the theory that the TI-85 can
"sacrifice" certain RAM addresses and not have problems. You could
dedicate a single address, say $8000, to the extra memory. Under
normal operation, the FPGA would monitor all accesses to this address,
and until a special "command sequence" is written to this address, it
behaves as if it were uninterupted SRAM. But once the command
sequence is written, you could then perform any sort of memory
swapping and expanding operations, and you could essentially have
unlimited SRAM or I/O port expandability features that use a minimal
amount of power, and is transparent to the user. You could even
dedicate a few of the FPGA I/O lines and connect these to the calc's
linkport so that you can download the required assembly driver if your
calc crashes.
I can see a system like this costing under $40 and using a very small
amount of power with unlimited memory expandability, operating at CPU
speed. The problem though, as I said before, is installation and
construction... Virtually NO electronics hobbiest would have the
ability to install this thing, much less build the PCB. So oh well.
-Mel
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