Re: TI-H: Power PC
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Re: TI-H: Power PC
>> Just by hearing the name PowerPC, you know its better than any Intel or
>> compatible. The PPC uses RISC technology (~4 years old) and the intel
>> processors use CISC technology (~22 years old). For one thing, the C
>> stands for complicated and the R stands for reduced. If you want, I can
>> show you a programming example for each in machine code and you can see
>> which can do the same process faster.
>
>Ummm... CISC stands for Complex Instruction Set Computer. Complicated
>and Complex have different connotations.
>
>Both CISC and RISC machines have their advantages. Modern Intel
>processors
>grow more RISC-like every year, and most AMD processors are fully RISC
>already. The line between the two is growing very thin, even the Atmel
>AVRs have multiply routines and they are RISC. Some ancient CISC
>processors don't even have multiply instructions. When you say that
>RISC is 4 years old, I am a bit curious as to how you arrived at
>that number. The z80, for instance, is technically a CISC processor
>but its instruction set is in many ways less useful than the AVR
>RISC set.
Heh..
Why don't I paste an exerpt from an article on embedded system design
I'm going to be submitting to the "IEEE Potentials" journal, just so a
few things may be cleared up:
----
Besides a shift towards the Harvard architecture, another
more important trend in microcontroller design is
designing with RISC (reduced instruction set). In the past,
microprocessor instructions have been CISC
(complicated/complex instruction set) which means that each
instruction that the microprocessor executes performs a
relatively complex function. These instructions generally
take more than a single clock cycle because of their
complexity. The RISC idea is to use simpler instructions
but execute them faster (usually in a single cycle), with a
penalty in program size because each instruction does less.
While in-theory RISC is a good idea, it is generally never
used, even in fast 32 and 64 bit microprocessors. A
successful "middle ground" between RISC and CISC has been
reached, and generally this is employed. Even though RISC
processors are supposed to have fewer instructions than a
comparable CISC processor, often times a RISC processor
will actually have more instructions.
Modern RISC architectures usually employ a "register to
register" scheme. The typical CISC processor may have
between 3 and 8 internal registers which instructions can
use, but modern RISC architectures use between 16 up to 256
registers, each individually accessible by every
instruction. With so many registers, data and operands can
be kept within the processor and can reduce the number of
off-chip memory accesses, which are usually much slower, and
this results in a vast speed improvement. This is
especially useful when executing code compiled from high
level languages. Even though these RISC instructions can
be nearly as complex as a CISC instruction, they suffer no
loss in speed because each RISC instruction takes an equal
number of clock cycles. This means that instructions can be
prefetched into an "instruction queue" and decoded before
the current instruction is even finished. This technique is
called 'pipelining' and can increase the speed of execution
by as much as ten times, depending on processor speed and
other factors. Since RISC instructions can be pipelined, it
seems as though a RISC instruction executes in a single
clock cycle even though it really doesn't, since RISC
instructions are executed in a parallelized fashion. CISC
instructions in simpler microprocessors are usually never
pipelined because each instruction requires vastly different
execution times, and coordinating these execution lengths is
impractical. Even this trend is changing, however, as
evident with the Pentium and Coldfire (among others)
architectures which are technically VLW (Very Long Word)
RISC which have CISC-like instructions.
----
You can see an older version of this document at
http://www.egr.msu.edu/~ee482/appnotes/incoming/tsaimelv/appnote.html
>Irregardless, the mac OS is a bloated, patronizing and, in my
>experience, very unstable system.
Listen to bryan on this one. He is wise. Vewy vewy wise. :)
-Mel
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