[A89] Re: Quite in here... let's discuss something!
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[A89] Re: Quite in here... let's discuss something!
No, the read cycles to fetch instruction from RAM are included. The
instruction move.l d0,d1 costs 4 clocks, just because it costs 4 clocks to
do one read-cycle(the reading of the instruction). But maybe your version
IS better, because bus is only used one time with add.l, and with LEA two
times. With ADD it just has to do more internal things. BTW I have some
questions about that, maybe someone knows the answer:
How does the DMA of the LCD work? And is there a chance for waitstates(slow
RAM)? And what happens if the LCD driver is bus master? Does the processor
just nothing then? What happens when a BR is requested between 2 read/ write
cycles form one instruction? Does it just interrupt the execution of that
instruction, let the requesting device do his bus work, and after that
continue with the instruction? And when an instruction first reads and then
does some internals in the processor, can the processor do that internal
things while another device is bus master after that read?
Pffffff that are a lot of questions I hope someone can answer......
Bye
Cheiz
----- Original Message -----
From: Samuel Nyall Stearley <sstear70@calvin.edu>
To: <assembly-89@lists.ticalc.org>
Sent: Monday, April 29, 2002 4:27 PM
Subject: [A89] Re: Quite in here... let's discuss something!
>
> What I have always wondered is if those clock cycles given in various
books
> takes into account the time to fetch the instructions from ram. They
might
> just be how long they take to acomplish in the processor once the
instruction
> fetch is done. So if you can reduce the code in the loop, then you have
> reduced the time in the instruction fetches, and so the loop runs faster.
So
> then the moveq #30,dx would be an optomization.
>
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