Re: A89: Starting out assembly, need help

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Re: A89: Starting out assembly, need help



>
>>>
>>>1 2 3 4 5 6 7 8 9 10
>>>IF ID EX MA WB
>>> IF ID EX MA WB
>>> IF ID EX MA WB
>>> IF ID EX MA WB
>>> IF ID EX MA WB
>>> IF ID EX MA WB
>>>
>>>IF -- Instruction fetch:  The processor reads the pc and finds the next
>>>instruction.
>>>ID -- Instruction decode:  Look at the instruction and figure out what it
>>is
>>>EX -- Execute:  If it is an add, do the add.  If it is a load or store do
>>>the effective memory calculation
>>>MA -- Memory access:  If it is a load or a store, access memory.
Otherwise
>>>do nothing
>>>WB -- Write the calculated value back to the destination register
>>>
>>
>>This pipeline model does not apply to any CPU of the m68k series. Probably
>>it
>>doesnt apply to any cpu at all. Usually the Memory Read takes please
before
>>instruction execution. (would make no sense otherwhise)
>>
>>memory accesses are usually also split up in reads and writes. Reads take
>>place
>>before the ex-stage and write take place in the wb stage.
>
>I should clarify:
>
>Registers are read in the ID stage, but RAM is read/written in the MA
>stage.  The WB stage is where the registers are written.  This pipelining
>model only applies to either the 1st or 2nd (I'm pretty sure the first)
>model in the m68k series.  The next version worked around this problem and
>later PPC chips even execute 2 instructions simultaniously, along with the
>pipelining.


Ok well. I wonder how Instructions like add.l d0,(a0)+ are executed then ?
IE before MA doesnt work quite well then :)

The pipeline you described is a MIPS R2000/R3000 pipeline (now I got it :) )
Its works nicely with a RISC design like the r2000 (seperated load/store),
but not with a CISC design like the 680x0.

Btw: The PPC604 is even able to execute 4 instructions simultaniously. The
68060 is
able to execute two instruction per cycle.

However the R2000 is from 1988 and the 68000 is from 1979. Full pipelining
in CPUs wasnt really an issue back in that time. However the 68000 used some
simple two stage pipeline which allowed fetching the next instruction while
the
current is being executed. But even the 6502 does that...

The full Instruction execution timings of the 68000 are in the user manual.
There is
no evidence of pipelining in them. (Otherwhise there would be latency cycles
etc..)

You should get some of the 680x0 usermanuals. They can be downloaded at
motorola
for free. They even ship them for free. Motorola also offers a CD which
contains
all Coldfire and 68k series manuals (nice to avoid stacks of paper).
Ordering code is "CDISD/D"

>As to where I got it:
>
>I study computer architecture at UW Madison and have worked on assembly on
>the mac for about 3 years, MIPS for one, and am just learning x86 -- the

Oh right you had to study the r2000 architecture and r2000 assembler using
the emulator,  I guess :)

>devil architecture.  I have heard that the 89 has a custom made 68k
>variation, so it may not implement pipelining at all.


AFAIK its a 68000 with some onchip I/O.

Where I got it: I am studying EE/CS. I started with 6502 assembler nine
years
ago, 68000 and x86 assembler five years ago. I owned and programmed
machines with various 6502 variants ,68000,68020,68030,68040,68060,
P54c,P55c and P2.
In most cases I did highly speed optimized multimedia programming. I also
did
some Z80, PIC (MPU) and PPC assembler programming.