Re: A89: Starting out assembly, need help
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Re: A89: Starting out assembly, need help
>>
>>1 2 3 4 5 6 7 8 9 10
>>IF ID EX MA WB
>> IF ID EX MA WB
>> IF ID EX MA WB
>> IF ID EX MA WB
>> IF ID EX MA WB
>> IF ID EX MA WB
>>
>>IF -- Instruction fetch: The processor reads the pc and finds the next
>>instruction.
>>ID -- Instruction decode: Look at the instruction and figure out what it
>is
>>EX -- Execute: If it is an add, do the add. If it is a load or store do
>>the effective memory calculation
>>MA -- Memory access: If it is a load or a store, access memory. Otherwise
>>do nothing
>>WB -- Write the calculated value back to the destination register
>>
>
>This pipeline model does not apply to any CPU of the m68k series. Probably
>it
>doesnt apply to any cpu at all. Usually the Memory Read takes please before
>instruction execution. (would make no sense otherwhise)
>
>memory accesses are usually also split up in reads and writes. Reads take
>place
>before the ex-stage and write take place in the wb stage.
I should clarify:
Registers are read in the ID stage, but RAM is read/written in the MA
stage. The WB stage is where the registers are written. This pipelining
model only applies to either the 1st or 2nd (I'm pretty sure the first)
model in the m68k series. The next version worked around this problem and
later PPC chips even execute 2 instructions simultaniously, along with the
pipelining.
As to where I got it:
I study computer architecture at UW Madison and have worked on assembly on
the mac for about 3 years, MIPS for one, and am just learning x86 -- the
devil architecture. I have heard that the 89 has a custom made 68k
variation, so it may not implement pipelining at all.
--Nate
References: