Re: Re: A86: Questions on Port 3, calc on, off, APD, etc

[Prev][Next][Index][Thread]

Re: Re: A86: Questions on Port 3, calc on, off, APD, etc


>I don't know what book he was refering to, but I have read several on the
>subject.  Two that stand out are Peter Norton's Inside the PC, and The
>Peter Norton PC Programming Bible.  These books have much info on the Intel
>based PC:
>
>Interrupt 2 on the PC, which has 256 vectored software interrupts, is the
>NMI interrupt.  This NMI bypasses the regular PIC interrupt controller.  It
>is used by the hardware to signal that memory has not been refreshed or is
>otherwise corrupted.  It is normally tied to a BIOS routine that gives a
>"PARITY ERROR" message, then halts the computer.  I've seen this on my old
>8088 based IBM PC immediately after pulling the memory expansion card;  I'd
>forgotten to turn off the computer first.  It also occurs when a device
>conflicts with memory--like a game controller card.
>
>On IBM PS/2 systems, with Microchannel architecture, there is a Timer Mode
>3 (0-2 are on all PC's) that is also tied to the NMI.  It can be used by
>the operating system as a watchdog to make sure a task like a timer tick
>handler doesn't take too long and crash the entire system, since most ISR's
>cannot be re-entered.
>
>But since this doesn't have much to do with A86 programming,  I'll let you
>read the books for yourselves.


:-)

Programming for the PC is kind of dull, because every program imaginable has
already been made, and there is just too much competition. Plus ASM rarely
applies to PC programming nowadays, except maybe for display drivers or
whatever. It is nice programming for a platform that is challenging, but not
overwhelming. It is nice squeezing the last drop of speed out of
the Z80.. All the brute speed on the PC leads to bad programming habits and
lack of optimization for many programs. Plus this Segment Offset crap just
complicates programming. It is understandable to have memory divided on, for
example, the TI-86 since the CPU can only address 64K at once, 2^8..... but
damn come one a 32-bit processor? 2^32 = 4,294,967,296 bytes. If I recall a
16-bit segment and a 16-bit offset overlap to form a 20-bit address which is
where this 1 meg barrier comes from. I am not even sure how more then 1
megabyte is accessed, anyone remember?

Later,
    Matt
Follow-Ups: