Re: A86: TI-86 interrupts, Part 2

To: assembly-86@lists.ticalc.org
Subject: Re: A86: TI-86 interrupts, Part 2
From: Pat Milheron <pmilheron@ti.com>
Date: Mon, 20 Jul 1998 13:13:52 -0700
Conversation-Id: <35B2220E.4D40DE42@flash.net>
Delivered-To: assembly-86-outgoing@towerguard.unix.edu.sollentuna.se
In-Reply-To: <35B2220E.4D40DE42@flash.net>
Reply-To: assembly-86@lists.ticalc.org

Wwy don't you try using the graph back up screen as a cache area
so that you can use the ROM routines that block move to and
from RAM. I had posted documentation on these already but I will
attach it to this posting again.

Later,
Pat

------------------
Original text

From: Bryan Rittmeyer <bryanr@flash.net>, on 7/19/98 12:42 PM:

TGaArdvark@aol.com wrote:

> Told'ja so! :-)

I don't suppose you know an easy way to handle paged RAM byte-wise
access other than to push af \ push hl and then pop them before
every _load_ram_ahl do you? Its getting to be a HUGE pain. The
E2 driver code is finished, but the memory access is extremely
erratic. I'm not even sure _load_ram_ahl itself is doing what
I think it is supposed to. Maybe its time to do some more ROM
dissassembly :-\

Bryan

-- 
Bryan Rittmeyer
mailto:bryanr@flash.net
http://www.flash.net/~bryanr/

ti86abs.inc

References:

Re: A86: TI-86 interrupts, Part 2

From: Bryan Rittmeyer <bryanr@flash.net>

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