Re: A86: a question
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Re: A86: a question
At 20:30 1998-04-19 -0500, you wrote:
>Could someone please explain what "T states" mean in relation to Z80
>processor speed? I looked it up in the Z80 reference book from Zilog, but
>it didn't explain it.
>
>I've never seen "T states" or anything like that when "counting cycles" for
>the PC (which varies greatly from processor to bus to cache), so does it
>have to do with bus i/o "cycle eaters"?
"Programming the Z80" by Rodney Zaks, which is -
as I've said before - an excellent book, and it describes _very_
good how the Z80 works internally. If you understand how the Z80
_really_ works, asm programming is a piece of cake... :) Below
is an example on how the execution of an instruction is done,
and hopefully it gives a better understanding what machine cycles
and T states are...
Each _machine cycle_ (or just 'cycle') contains several T states
(3-5 depending on the instruction). Each T state takes equal
time to execute (1000/MHz nanoseconds, thus about 166ns on a
6 MHz Z80). But machine cycles are executed at different speeds,
depending on how many T states they use.
At the beginning of each instruction, the instruction must
be fetched from the RAM. The three first T states in the first
machine cycle of that instruction (T1, T2, T3 in M1) are use to
fetch and the decode the instruction (the first opcode that is):
T1: PC OUT - Transfer Program Counter to the Address Bus
T2: PC=PC+1 - Increase Program Counter
T3: INST into IR - Transfer memory byte to Instruction Register
(an internal register)
After that, the processing is done. A very good example on how
the CPU works, is the instruction ADD A,r (for instance, ADD A,B):
T4: (B) -> TMP, (A) -> ACT
TMP and ACT are two internal registers, which are the two arguments
to the ALU (arithmetic-logical unit) which does the calculating.
Note that these two transfer are done simultaneously. That's because
they use different paths within the system (which is obvious by
looking at the internal organization - get the book!!).
Now, the addition does NOT take place in T5 - it waits until the
next machine cycle, and skips T1 of M2 as well:
T2 of M2: (ACT) + (TMP) -> A
Why? Assume it had been done in T5 of M1. The instruction would require
5 T states then. But since the CPU "knows" that the first three
T states of every instruction involves in reading a byte from the
RAM, the databus is free to use. In short, the end of the ADD instruction
is done while fetching the next instruction - CLEVER!!! That's called
fetch-execute overlap. In this case, it saves 20%.
The addition must take place in T2 of M2, not T1, because then the data bus
is used to carry status information out (not exactly sure what that is).
Another example is LD C,D. That instruction uses all 5 T states of M1.
T4 of M1 copies D into TMP, and T5 copies TMP into C. It _must_ use
TMP because it's not possible to both read and write into, or from,
the RAM at two different locations (all internal registers are
a port of the RAM).
So, LD C,D is slower than ADD A,B in a program (5 vs 4 T states) although
the latter instruction actually uses more than 4 T states (but they're
overlapped).
LD C,D can't overlap, because (I think), the register block is used
in T1 and T2 (fetch PC and inc PC) and the databus is used in T3.
The A register is NOT in the register block - it is much closer to the
ALU (it's more like an internal register).
But the instruction LD A,C should be able to overlap.... but it doesn't :-/
>Please confirm this understanding: a microprocessor's MHz is how many
>million cycles it executes per second...a 6 MHz processor like the TI-86's
>runs 6,000,000 cycles per second. An instruction that executes in 5 cycles
>could be executed 1,200,000 times second. But this seems a little too fast
>for the calc, but not my 50 MHz 486.
It's 6,000,000 T states per seconds, not cycles.
--
Real name: Jimmy Mårdell
IRC......: Yarin
Email....: mailto:yarin@acc.umu.se <-- NEW E-MAIL ADDRESS!!!!
Homepage.: http://www.algonet.se/~mja/
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