LZ: Re: RAM EXPANDER IMPORTANT ANNOUNCEMENT -- Please
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Alright! I don't mind a delay as long as you make it worth while!
Bi-directional parallel ports on newer cards supporting the 16550 serial
chip are EPP ports right? Also, you could solder on a Serial Flash chip
for the first meg then have another chip, for the second meg, a RS232 port
(for modems and mice and whatnot!), a passthru port for another calc to
access or for this calc to access another device such as the computer, all
together or have a combo of those and other memory banks! I suppose the
method being used is sort of like parallel processing, and 50-60kb/s!
That's like more than 2x faster than a 28.8! Haha! Think about a TI-Calc
ISDN line! Also, you did
mention something about bringing data from the expander into internal
memory to handle; can't you just leave it on the expander? Then we can
have 512kb programs and such (which would be what you'd need for a TCP/IP
interface or graphical and power OSs along with that)! Wow! Now you can
have your choice of Windows 8X, OS/8X, Linux85, DOS 8.5 and such! HAHA!
This is great!
"Honors Master PhD of Idea Engineering"
-= Zenon@bbs.nexes.com =-
----------
: From: list-zshell@lists.ticalc.org
: To: Zenon
: Subject: LZ: RAM EXPANDER IMPORTANT ANNOUNCEMENT -- Please
: Date: October 16, 1996 7:00 PM
:
:
: I know that many of you are anxious to see the final schematics, but
: I'm sorry but I've made some major developments, and I'll have to
: delay even further.
:
: I figured out the problem with my simplified design. I now know that
: the expander can be built with a single chip in addition to the serial
: flash chip, and the board footprint will be around 1/2.5".
:
: Like I mentioned in the last message, this base design suffers from a
: race problem in which the setup times cannot be met. However, I fixed
: it by making it asynchronous using an RC circuit. I haven't actually
: built the final "one chip" version yet, but there's absolutely no
: reason why it won't work.
:
: This brings me to the point of this message. ****I have now
: discovered a totally new way to synchronously design the circuit!****
: This has hundreds of implications for the expander. First, this means
: that there's now almost no limit to the transferr rate. The
: difference between the asynchronous and synchronous version will be
: only 1 or 2 kilobytes per second, but that's only on a "regular"
: TI-85. On a turboed calculator, I forsee huge transferr rates,
: probably on the order of 6-9 kilobytes per second. The rate could be
: double that on the TI-92, and if you've got an enhanced parallel port
: (EPP), quadruple that with a direct expander-computer link.
:
: Another implication of the synchronous design is that this allows for
: an I/O expansion with absolutely no loss in speed. To this you could
: even add a second serial flash chip! This means that you can have a
: total of 2 megabytes of storage, each of which is accessed at the
: exact same speed, **DOUBLING** the effective transfer rate! Instead
: of a second serial flash chip you could add all sorts of other stuff,
: like an integrated RS-232 serial port, a matrix keyboard, etc, and you
: will be able to access them simultaneously with the serial flash chip
: (again, with no loss in speed). A serial port will be a definite
: plus, because then (with appropriate software) very large terminal
: programs could be written, maybe even a TCP/IP winsock so don't have
: to use Lynx!
:
: This design is completely scalable, and with circuit modification you
: can add an UNLIMITED amount of Serial Flash chips! It will be VERY
: easy to scale the design up to 4 memory chips (or 1 chip with 3 ports,
: 2 chips with 2 ports, etc). Past 4 megs, though, the logic gets
: exponentially more complicated, so this will only be for die-hard
: users who want to do some extreme calculating. Accessing 4 chips
: simultaneously will result in a small loss of speed, but it probably
: won't be noticeable.
:
: I haven't built nor tested the synchronous design, but I've learned so
: much about this stuff that I'm sure it will work (I'll have the
: prototype done by this weekend). It will be only slightly more
: complicated (I estimate about 3-4 logic chips for 2 megs), but the
: advantages make it worth it.
:
: As soon as I'm done building and testing all the versions, I'll
: release two schematics. The "Expander Lite" will be my original
: design. It will pretty simple to build, comsume very little power,
: and be relatively small and cheap. Like I said, the disadvantage of
: this will be that there's a definite ceiling to the transferr rate,
: and there's no room for I/O expansion.
:
: I'm calling the synchronous design the "Expander MT" (guess what MT
: stands for...!). It will have a more complicated PC board, cost about
: $30 to $50 more (if you want two megs total), and consume more power.
: If you want you can omit the I/O port and just have a single flash
: chip. The absolute upper limit to the transferr rate will be around
: 50-60 kilobytes per second, but only the computer-expander link will
: even get close to this rate. This is best for people who value speed,
: power and expandability.
:
: The two versions will be accessed differently, so there will have to
: be two versions of the software (or I can just make it an option in
: the software to select your version of Expander).
:
: Sorry about all the delays in the schematics, but I believe they're
: necessary so that we can all get the best design possible. I've been
: getting an extreme amount of homework lately, so that's why
: development has been slow. Starting next week, however, I can devote
: a lot more time to this. If you're absolutely dying to find out
: exactly how I'm acheiving the synchronous design, email me, but the
: details will probably just confuse most people.
:
: -Mel
:
: --
: The TI Memory Expansion Homepage
: http://pilot.msu.edu/user/tsaimelv/expander.htm
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