LZ: Ram Expander Update.

[Prev][Next][Index][Thread]

LZ: Ram Expander Update.

The following is a short project status update:


I finally got a few hours of free time today, so I decided to start
testing the expander at full speed.  For some reason my prototype
board burnt out (note to experimenters:  when something starts to
smoke, turn it off!), and I got a nasty burn from the voltage
regulator because something wasn't hooked up right.  Man, a 9V battery
can sure put out a lot of heat!  I rebuilt it on an experimenter's
breadboard.  I hooked it up, wrote a simple Get-Status and
Write-Enable program, and ran it. =20


I manually tweaked the value of the RC time delay just enough so that
data is latched properly, and when I tested the program at maximum
speed, it didn't work.  I slowed it down approximately 3 times using
NOP instructions, and it worked correctly!  The routine sent a bit in
approximately 100 T states, which translates to a raw data rate of
almost 7500 bytes per second!!!  That's also just with an unoptimized
routine, so the raw data rate could be even higher.


Now, the "real" data rate will be slower, since the chip has a
page/read and write setup time of anywhere from 400 to 5000
microseconds, and the routine must do something useful with the data.
Nonetheless, the data rate of the final version of the expander should
be MUCH faster than regular calc to calc transferrs.  With a lot of
optimization and a little luck, real-time video may soon be possible.


If I could figure out a way to make synchronous operation possible, a
turboed calc could theoretically send/receive at over 12k per second!
However, the simple fix for the expander is asynchronous operation, so
the data rates between regular calcs and turboed calcs should be about
equal (I'm estimating 3k-5k per second, but don't quote me).  If I
ever figure out to run this thing synchronously, we're in business!
(actually, I've been playing around with a totaly new idea, and I
think it's possible, but I'm not sure.)


I think I've finalized the design I'm going to use, but I'm still
searching for better ways of doing this.  I attempted to build it
using a greatly simplified method (only one chip!), but it didn't work
right.  In retrospect I think I made an error, and tomorrow I'll
rebuild it and test it again.  I think it's very important that I know
I have the best design before I release any schematics, because if I
find a much better way of doing something, some people may be screwed
because they've already built an "inferior" version.


-Mel


<pre>
--
The TI-85 Memory Expansion Homepage
http://pilot.msu.edu/user/tsaimelv/expander.htm
</pre>