[A83] Re: AGAIN!!!!!!!!!!!!!

To: <assembly-83@lists.ticalc.org>
Subject: [A83] Re: AGAIN!!!!!!!!!!!!!
From: "David Phillips" <david@acz.org>
Date: Sun, 28 Jul 2002 08:19:06 -0500
References: <000201c23602$cc8b9750$0201a8c0@ELMO> <041d01c23608$d09b1d60$3e891581@BSTERNERL> <000d01c23613$10bb8b00$6401a8c0@myuj3o9h2i80m2>
Reply-To: assembly-83@lists.ticalc.org


The answer to your real question is yes, regardless of which way disabled
interrupts are handled.  If interrupts are disabled, you miss any that
occur.  There is no queue for them.

The answer to your first question is that the CPU takes care of blocking
interrupts.  Hardware devices are not affected.  All architectures that I
know of are like this.  Having the CPU tell hardware devices to not send
interrupts would be very difficult and error prone.

If you read Zilog's documentation for the CPU
(http://www.zilog.com/docs/z80/um0080.pdf), then you will find the answer
(page 192):

"DI disables the maskable interrupt by resetting the interrupt enable
flip-flops (IFF1 and IFF2).  Note that this instruction disables the
maskable interrupt during its execution."

"When the CPU executes the instruction DI the maskable interrupt is disabled
until it is subsequently re-enabled by an EI instruction.  The CPU does not
respond to an Interrupt Request (INT) signal."

> And BTW - I doubt anybody on this list will know, but I have a question.
> When you disable the interrupts via 'di', does the CPU simply ignore any
> interrupts that are triggered? or does the piece of hardware that
triggeres
> the interrupts simply stop it's internal timer?  I guess what I'm trying
to
> say is if you di, do you miss any interrupts?

References:

[A83] Re: AGAIN!!!!!!!!!!!!!

From: "Scott Dial" <scott@scottdial.com>

[A83] Re: AGAIN!!!!!!!!!!!!!

From: Brandon Sterner <bms9019@rit.edu>

[A83] Re: AGAIN!!!!!!!!!!!!!

From: "Joe Pemberton" <joe@joepnet.com>